PWM Strategies for Full-Bridge Inverter

Chapter 01

Full Bridge Inverter

In a full bridge inverter, we have an input voltage ($v_{in}$) which is DC, and an output voltage ($v_{out}$) which is AC. In between we have a full bridge, consisting of two legs, 1 and 2. Each leg has two switches, one upper and one lower. Both legs are identical, so when I refer to leg x, x is either 1 or 2.

If we look at leg x, we have the gate signals $S_x$ and $\overline{S_x}$. The overline means that the gate signal is inverted. Meaning that the upper and the lower switches are never on at the same time. In practice you also include a dead time, where both switches are off, but this does not matter on a high level. The modulation voltage of leg x ($v_{m,x}$) is the voltage between the switches in leg x. $v_{m,x}$ can be controlled by controlling $S_x$ and $\overline{S_x}$.

Full bridge inverter

The goal of the bridge inverter is to control $v_{m,1}$ and $v_{m,2}$ such that $v_{out}$ becomes a sine wave. $v_{out}$ is given by:

$$v_{out} = v_{m,1} - v_{m,2}$$

$v_{m, x}$ is either 0 or $v_{in}$, depending on whether the switch is on or off:

$$v_{m, x} = \begin{cases} 0 & S_x = 0 \\ v_{in} & S_x = 1 \end{cases}$$

which is equivalent to:

$$v_{m, x} = S_x \, v_{in}$$

Inserting for $v_{m,1}$ and $v_{m,2}$ into the equation for $v_{out}$, we get:

$$v_{out} = S_1 \, v_{in} - S_2 \, v_{in} = (S_1 - S_2) \, v_{in}$$

This means that $v_{out}$ could be 3 different values:

$$v_{out} = \begin{cases} v_{in} & S_1 = 1 \textrm{ and } S_2 = 0\\ 0 & S_1 = S_2\\ -v_{in} & S_1 = 0 \textrm{ and } S_2 = 1 \\ \end{cases}$$

By switching $S_1$ and $S_2$ in a certain pattern, we can make $v_{out}$ on average a sine wave, as shown in the figure below. By filtering vout you will get a sine wave. The filter can be made using inductors and capacitors.

A PWM is required to generate the gate signals $S_1$ and $S_2$. In the following sections 3 methods will be explained and compared. The 3 PWM methods are:

  1. Bipolar PWM
  2. StandardUnipolar PWM
  3. Fast-slow leg PWM

But first, let's explain how a PWM works.

Chapter 02

How PWM Works

Half-bridge — one leg of the inverter

If we just look at one leg of the bridge, as shown in the figure above. We want to control $v_{m,x}$ by controlling the gate signal ($S_x$). The problem is that the gate signal ($S_x$) is binary, so it can only be 0 or 1. The solution is to define a duty cycle ($D_x$) as the average gate signal ($S_x$) over one switching period.

Thus, if we want a duty cycle ($D_x$) of 75%, the gate signal ($S_x$) should be 1 for 75% of the time and 0 for the other 25%.

A PWM is a way to convert a duty cycle into a gate signal. There are different ways to do this, but it is most common to compare the duty cycle ($D_x$) with a carrier signal. We will be using a triangular carrier signal, the frequency of the carrier signal is the switching frequency.

The idea is that when the duty cycle ($D_x$) is higher than the carrier signal, the gate signal ($S_x$) should be 1, and when the duty cycle ($D_x$) is lower than the carrier signal, the gate signal ($S_x$) should be 0:

$$S_x = \begin{cases} 1 & \text{if } D_x > \text{carrier} \\ 0 & \text{otherwise} \end{cases}$$

This is also shown in the Figure below:

However, we want to control $v_{m,x}$, let's say that we have a reference voltage ($v_{ref}$) for $v_{m,x}$. Then we want to calculate the duty cycle ($D_x$) given a reference voltage ($v_{ref}$). $v_{m,x}$ is given by:

$$v_{m,x} = v_{in} \, S_x$$

On average we want $v_{m,x}$ to be equal to $v_{ref}$, and $S_x$ to be equal to $D_x$:

$$v_{ref} = v_{in} \, D_x$$

Solving for the duty cycle gives:

$$D_x = \frac{v_{ref}}{v_{in}}$$

As long as D_x is between 0 and 1, we can control $v_{m,x}$ to be equal to $v_{ref}$ on average. This means that the reference voltage must be between 0 and $v_{in}$:

$$0 \leq v_{ref} \leq v_{in}$$
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